1. Field of the Invention
The present invention relates to a semiconductor memory device and its manufacturing method.
2. Description of the Background Art
A MONOS (Metal Oxide Nitride Oxide Semiconductor) transistor is mentioned as one of transistors (memory transistors) employed for memory cells of non-volatile memories (“Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?”, by Boaz Eitan et al., Technical paper presented at the International Conference on Solid State Devices and Materials (Tokyo, 1999), SSDM 1999, for example). This MONOS transistor has a source region and a drain region formed in a semiconductor substrate, a gate insulating film formed on the semiconductor substrate and a gate electrode formed on that gate insulating film. The gate insulating film of the MONOS transistor is a laminated film (ONO (Oxide Nitride Oxide) film) that a silicon nitride film is sandwiched between silicon oxide films.
The MONOS transistor retains memories by accumulating an electric charge in a trap in the silicon nitride film of the ONO film. Moreover, there is a so-called multi-bit MONOS transistor which can retain two bits of the memories in one cell by accumulating the electric charge partly in two parts in different places from each other in one MONOS transistor (called as a NROM). Accordingly, with regard to the MONOS transistor, it is possible to make a cell area per one bit be sharply smaller as compared with conventional floating gate type memory transistors and so on. Moreover, it also has a feature that it is easy to form by reason of simplicity of its structure and also has a feature that there is little leakage of the electric charge by reason that the electric charge is accumulated in the insulating film (the silicon nitride film), thus it has a high reliability.
In the meantime, a “fieldless array” is known as a structure of memory cell arrays of the non-volatile memories (U.S. Pat. No. 6,174,758, for example). This fieldless array is defined as an array that a field oxide film is not employed to isolate respective elements constituting the array. With regard to the fieldless memory cell array, the filed oxide film is not necessary between the memory transistors, thus the memory transistors can be placed in the semiconductor substrate at high density, and a reduction of a forming area of the memory cell array can be planned.
As described in U.S. Pat. No. 6,174,758, a bit line is a diffusion wiring (a diffusion bit line) formed in the semiconductor substrate in the conventional fieldless memory cell array. The diffusion wiring has a high resistance as compared with a metal wiring, thus the resistance of the bit wiring becomes large, especially when the memory cell array becomes large in scale in the memory cell array having the diffusion bit line. Accordingly, contacts connected with wirings in an upper layer are formed at intervals of several to several tens bits of the cells on the diffusion bit line to cover an influence of the high resistance of the diffusion bit line and to plan a reduction of the resistance of the bit line, conventionally. That is to say, it is necessary for the memory cell having the conventional fieldless array structure to secure a region to form the contact on the diffusion bit line. This prevents the reduction of the forming area of the memory cell array.